This is a real CPU — built from registers, ALUs, muxes, and memory, simulated cycle by cycle in your browser. Write code in C, C++, Rust, or assembly, compile it, then step through each clock cycle and watch instructions flow through the pipeline.

Simten
RV32I CPU
Pipeline
FetchIF
————
DecodeID
————
ComputeEX
————
MemoryMEM
————
SaveWB
————
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Disassembly
Compile code to see disassembly
Registers
zero0x00000000
a00x00000000
a10x00000000
a20x00000000
a30x00000000
a40x00000000
a50x00000000
a60x00000000
a70x00000000
t00x00000000
t10x00000000
t20x00000000
ra0x00000000
sp0x00000000
t30x00000000
t40x00000000
t50x00000000
t60x00000000
gp0x00000000
tp0x00000000
s00x00000000
s10x00000000
s20x00000000
s30x00000000
s40x00000000
s50x00000000
s60x00000000
s70x00000000
s80x00000000
s90x00000000
s100x00000000
s110x00000000