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Articles about hardware design, simulation, and the tools we're building.

Infer everything from one object literal

How one generic call lets a callback know the types of the keys next to it. It's what Zod and tRPC do, and two parts of it are genuinely fiddly to get right.

EngineeringTypeScript

Pong in Hardware

A complete Pong game built from logic gates, registers, and memory — two paddles, a bouncing ball, and a 14-phase rendering pipeline, all without a CPU.

Game~80 nodes

Snake in Hardware

A complete Snake game built entirely from logic gates, registers, and memory — no CPU, no software, just digital circuits.

Game~100 nodes

Building a CPU from Scratch

From NAND gates to a working processor — fetch, decode, execute, all built from logic gates you can click.

CPU~300 nodes

How TPUs Do Calculations

Inside Google's Tensor Processing Units: a 2x2 systolic array built from logic gates. Watch matrix multiplication happen one clock cycle at a time.

Accelerator~60 nodes

Computing Trig in Hardware

How calculators and GPUs compute sine and cosine using only bit shifts and addition — the CORDIC algorithm, built from logic gates.

Accelerator~40 nodes

Sorting Networks

A fixed wiring of comparators that sorts any input in the same number of steps — no branches, no loops. The algorithm behind network switch fabrics, GPU sort, and median filters.

Accelerator~25 nodes

How Network Switches Work

Packet buffering, MAC address lookup, and forwarding — built from the same primitives as everything else.

Networking~50 nodes

Breakout in Hardware

A classic brick-breaking game built entirely from logic gates — ball physics, paddle control, brick collision detection, and score tracking, all without a CPU.

Game~90 nodes

AES in Hardware

Why Intel built AES into the CPU. SubBytes, XTime, and MixColumns — the operations behind the world's most deployed cipher, verified against FIPS 197.

Accelerator~60 nodes

ChaCha20 in Hardware

The TLS cipher that encrypts most of the internet, built from logic gates. Explore the ADD-XOR-ROTATE quarter-round with live interactive circuits.

Networking~50 nodes

CRC-32 in Hardware

The checksum at the end of every Ethernet frame and ZIP file — a 32-bit shift register with XOR feedback, running in the NIC on your machine right now.

Networking~15 nodes

A RISC-V CPU That Runs C

A 5-stage pipelined RISC-V processor with data forwarding and hazard detection — write C, compile it, and step through execution cycle by cycle.

CPU~200 nodes